1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same, and more particularly to a semiconductor device including an interposer and a method for producing the semiconductor device.
2. Description of the Related Art
In recent years, semiconductor devices in a package have been densified, and, as a result, a chip mounting area has been continuously reduced. In the course of reaching such an achievement, a multi chip module (MCM) which is a package having multiple chips packed therein has been developed. In order to further increase the density in the MCM, a three-dimensional package in which semiconductor chips (dies) are stacked by providing a through electrode penetrating the semiconductor chips is now being developed.
An organic substrate having a through hole is usually used as a package substrate on which semiconductors are mounted in an MCM. Alternatively, in place of the organic substrate, a silicon substrate having a through electrode can also be used. The silicon substrate can be produced relatively easily in a silicon device production line, and can be processed with high accuracy because the production method of the silicon substrate is the same as that of a device chip. At present, a technique for forming a through electrode through a silicon substrate is relatively difficult to be performed. Accordingly, a silicon substrate has not so far been put into practical use as a package substrate for the MCM.
Furthermore, in order to use a silicon substrate as a package substrate in an MCM, the silicon substrate has to be able to be reliably mounted with devices included in the MCM.
One of breakdown modes that reduce the packaging reliability is electrostatic discharge (ESD) damage. The ESD damage is a phenomenon in which the insulating function of a device is destroyed due to defects in an insulating film in the device. Here, the defects are formed when electric charges accumulated in a chip passes through the insulating film. For example, in a complementary metal oxide semiconductor (CMOS) device, the ESD damage is prone to be caused because a gate insulating film has a low breakdown voltage. Accordingly, an MCM including such a device should have a configuration in which the ESD damage is not caused during the assembly process or the use of the MCM.
A conductor having a larger outer surface area accumulates a larger quantity of static electricity, when a module is charged. This is because, since the conductor builds a capacitor with the outside, the accumulation amount of electric charges is in proportion to the surface area of the conductor. When a silicon substrate is employed in a module, the silicon substrate is a conductor having the largest conductor therein. As a result, the substrate itself can be the largest current source in the module.
However If a silicon substrate has no through electrode, a thick insulating film can be provided to the entire surface of the substrate. The provision of such a film enables the silicon substrate to be separated from a wiring with very high dielectric strength. As a result, the silicon substrate does not cause any ESD damage. In contrast, if a silicon substrate has a through electrode, it is difficult to form a thick insulating film on the wall on which the through electrode is provided. Consequently, the distance between the substrate and a conductor pattern is short. Therefore, the flow of a high potential of the substrate due to static electricity may break the insulation between the substrate and the wiring. This phenomenon is caused by the package substrate made of a semiconductor.
A technology related to a wiring substrate using a silicon substrate described in Japanese Unexamined Patent Application Publication No. Hei 6-29456 (Patent Document 1) has been available. This document discloses a semiconductor wiring substrate provided with a through electrode for connecting multiple chips, and for collectively wiring external connection terminals. The semiconductor wiring substrate is mounted to cover from above multiple chips placed flat with the element-formed surface facing upward. The semiconductor wiring substrate connects the multiple chips to each other and includes a bonding pad for connection of the substrate with an external terminal. The bonding pad is formed on the top surface of the wiring substrate. According to the above document, an electrostatic protection circuit which is formed inside a chip in a conventional technology is formed on the semiconductor wiring substrate between the bonding pad and the connection terminal connecting the bonding pad to the chip.
In “The electrical transmission characteristics of the through electrode formed on silicon” by Tomonaga Kobayashi and four others, MES2004 (pp. 113-116), October, 2004, which reports to a study in a different technical field, electrical characteristics of a through electrode formed on a silicon substrate are evaluated. In the evaluation described in this document, a through electrode is mounted on a certain one of surfaces of the silicon substrate, and an impurity diffusion layer is formed on the opposite surface of the silicon substrate from the certain surface. By connecting the through electrode and the impurity diffusion layer electrically, the potential of the impurity diffusion layer is set to be a constant potential such as a GND potential and a power supply potential. This document also reports results from experiments and simulation in which the electrical transmission characteristics of the through electrode are examined by varying the potential of the impurity diffusion layer.
A conventional package substrate is usually an organic substrate as described above. For this reason, no evaluation has been made as to an influence of a conductive package substrate on the reliability in packaging. Against this background, in order to use a silicon substrate as a package substrate, it is now necessary to develop a configuration including appropriate means for dissipating a surge of static electricity caused by ESD. This is a critical problem to be solved in designing and producing an MCM.
To solve such a problem, it may be considered to provide a protective element on a silicon substrate as described in Patent Document 1. In such a configuration, a protective circuit utilizing a P-N junction is mounted as a protective element, as in the device. Since the protective circuit is located on the silicon substrate, it is necessary to perform a selective ion injection process multiple times in the production.
However, when a silicon substrate is employed as a package substrate, it is desirable that no formation of P-N junction be involved for the purposes of making the production process easier and of avoiding an increase in cost. Hence, it is required to develop a technology for solving the ESD problem with a configuration including no diode or transistor.